1. Field of the Invention
The present invention relates to a power-current measuring circuit for a burn-in tester, and more particularly to a power-current measuring circuit capable of satisfactorily measuring a power current which flows in each semiconductor integrated circuit formed on a wafer disposed in a burn-in tester which performs a burn-in test of the wafer on which the semiconductor integrated circuits have been formed and a power-current measuring method therefor.
2. Description of the Related Art
A process for manufacturing a semiconductor integrated circuit has been performed to maintain the reliability of products by applying power supply voltage to a plurality of semiconductor integrated circuit chips formed on a wafer disposed in a furnace of a constant temperature bath at a wafer level. Moreover, a test pattern signal corresponding to the type of the semiconductor integrated circuit chip is supplied to verify the operation (pass/fail) in a predetermined temperature environment. A burn-in test is performed as described above. The apparatus having a function of determining the pass/fail at the wafer level is referred to as a wafer-level burn-in tester.
The wafer-level burn-in tester incorporates a constant temperature bath with which temperatures and electric signals can be programmed. A multiplicity of test burn-in board (hereinafter called a "TBIB") on which the wafers are placed are loaded into the constant temperature bath. The TBIB in the constant temperature bath and an external tester are connected to each other through connectors provided for the constant temperature bath. A variety of test signals are transmitted/received through the connectors so that a burn-in test corresponding to the type of the chips placed on the TBIB is performed.
The burn-in test at the wafer level is performed such that measurement of a power current which flows in each semiconductor integrated circuit formed on the wafer is required to perform measurement of the power current for each chip and collective measurement of all of the chips or a plurality of the chips.
FIG. 2 shows an example of a power-current measuring circuit 100 for a conventional wafer level burn-in test. When the power-current measuring circuit 100 shown in FIG. 2 measures the power current of each chip on the wafer 20 mounted on the TBIB 19, the output of the power supply circuit 10 (in the foregoing case, a power supply circuit 10 incorporates only large-current measuring power supply circuit 10a having a large capacity with which all chips on the wafer 20 can be operated) is connected to each chip on the wafer 20 through a current-detecting resistor 11 and a wafer-chip selection circuit 15. A wafer-chip selection circuit 15 is connected to a control unit 22 through a bus (BUS). A chip on the wafer 20 instructed with a wafer-chip selection signal supplied from the control unit 22 is selected by wafer-chip selection switches 15a to 15n accommodated in the wafer-chip selection circuit 15. Thus, the power current output from the power supply circuit 10 is supplied to the selected chip.
The output of the power supply circuit 10 is as well as connected to a current measuring circuit 13 to which two ends and an input stage of the current-detecting resistor 11 are connected. The current measuring circuit 13 detects the differential voltage generated at the two ends of the current-detecting resistor 11 in accordance with the power current value communicated from the power supply circuit 10. The current measuring circuit 13 outputs a measured-current signal corresponding to the differential voltage to an A/D converter 18 through an AMP 17. The A/D converter 18 converts the measured-current signal input from the current measuring circuit 13 and formed into an analog fashion into a digital fashion and outputs a predetermined digital signal indicating the measured current value to the control unit 22 through the bus. Thus, the power current value can be measured.
The above-mentioned measurement of the power current at the wafer level is required to be capable of performing both of the power-current measuring test of all of the chips on the wafer 20 and the power-current measuring test of only one chip. The capacity of the power current which flows in the one chip on the wafer 20 and that of the power currents which flow in all of the chips are different from each other by several hundred times or greater. Therefore, it is preferable that the capacity of the power current of the power supply circuit 10 can precisely be set to be a wide range.
The conventional power-current measuring circuit 100 shown in FIG. 2, however, incorporates only the large-current measuring power supply circuit 10a having a large capacity with which all chips on the wafer 20 can be operated to serve as the power supply circuit 10. Therefore, the power currents which are required of both of the power-current measuring test of all chips on the wafer 20 and the power-current measuring test of only one chip and which are different from each other by several hundred times or greater cannot precisely be set. As a result, there arises a problem in that a required resolution accuracy for measuring the power current cannot be realized.
When the measurement resolution of the power-current measuring circuit 100 is adjusted to be capable of measuring the small power current of one chip on the wafer 20, an A/D converter having an excessively large number of bits and a current detection resistor corresponding to the large electric power is required. The foregoing specifications cannot be realized from a viewpoint of cost reduction.
Therefore, the structure of the conventional power-current measuring circuit 100 for the wafer-level burn-in tester suffers from a problem in that both of the measurement of the large current on the wafer and measurement of the small current of one chip cannot precisely be performed.